1. Technical Field
Embodiments of the present disclosure relate to semiconductor devices aligning data to receive and output aligned data.
2. Related Art
As semiconductor systems are developed to operate at a high speed, high data transmission rates (or data communication at high bandwidth) between semiconductor devices included in each semiconductor system have been in increasing demand. In response to such a demand, various pre-fetch schemes have been proposed. The pre-fetch scheme may correspond to a design technique that latches data inputted in series and outputs the latched data in parallel. An internal clock divider may be used to obtain the parallel data. If an internal clock signal is divided, a plurality of multi-phase clock signals may be generated and the plurality of multi-phase clock signals may be used in parallelization or serialization of data.